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GEZEL

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Project Description:

English:
(Last Update 2009-06-12 15:46)

GEZEL is a language and open environment for exploration, simulation, and implementation of cycle-true hardware models. The models can be simulated stand-alone, or cosimulated with one of the supported instruction set simulators. GEZEL models can be automatically translated into VHDL for hardware synthesis targeting FPGA or ASIC.

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Japanese: