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Project Description

By simulator + Tcl + C language, let's verify ASIC and FPGA effectively!

(simulator <= DPI-C => C++, simulator <= named pipes => C++ are under development, too.)

NOODLYBOX is a mimic processor for verification.

It can manipulate FPGA model which is connected to microcomputer's local bus.

Detail:

  1. A microcomputer and FPGA are mounted on a printed circuit board.
  2. A microcomputer and the connection form between FPGA are SRAM interface.
  3. FPGA is modeled by VHDL or Verilog.
  4. ModelSim, ISE Simulator, or Icarus Verilog are installed.

When all the conditions mentioned above are met, NOODLBOX can act as the substitute of the microcomputer on an HDL simulator.

System Requirements

System requirement is not defined

Released at 2008-11-16 02:16
noodlybox 0003 (1 files Hide)

Release Notes

NOODLYBOXの3回目のリリースです。
Repositoryのtrunk rev50に相当します。

ニュースに書いた、ISE Simulatorで結果が不正になる問題の対策を行いました。

また、ModelSIM上でfsm.tclを使う場合に、コンパイルが失敗したら実行をとりやめる機能を追加しました。

Changelog

機能リクエスト
#13952 compileoutofdate失敗でシミュレーション停止させる

バグ修正
#13971 ISE SimでのVHDL Simが不正な結果になる