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Project Description

By simulator + Tcl + C language, let's verify ASIC and FPGA effectively!

(simulator <= DPI-C => C++, simulator <= named pipes => C++ are under development, too.)

NOODLYBOX is a mimic processor for verification.

It can manipulate FPGA model which is connected to microcomputer's local bus.

Detail:

  1. A microcomputer and FPGA are mounted on a printed circuit board.
  2. A microcomputer and the connection form between FPGA are SRAM interface.
  3. FPGA is modeled by VHDL or Verilog.
  4. ModelSim, ISE Simulator, or Icarus Verilog are installed.

When all the conditions mentioned above are met, NOODLBOX can act as the substitute of the microcomputer on an HDL simulator.

System Requirements

System requirement is not defined

Released at 2009-12-12 11:44
noodlybox 0011 (1 files Hide)

Release Notes

This version is equivalent to "trunk rev133" in the repository.

"pipesample" was transplanted to VHDL. It can be executed by ModelSim.
Please refer to ImplementationByPipe for the details.

Repositoryのtrunk rev133に相当します。

pipesampleをVHDL(シミュレータはModelSim)に対応させました。
詳細はImplementationByPipeを参照してください。

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